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1 of 17 features ? 1128 bits of 5v eeprom memory partitioned into four pages of 256 bits, a 64- bit write - only secret, and up to five general - purpose read/write registers ? on - chip 512 - bit iso/iec 10118 - 3 sha - 1 engine to compute 160 - bit message au thentication codes (macs) and to generate secrets ? write access requires knowledge of the secret and the capability of computing and transmitting a 160 - bit mac as authorization ? secret and data memory can be write protected (all or page 0 only) or put in ep rom - emulation mode (write to 0, page 1) ? unique, factory - lasered and tested 64 - bit registration number assures absolute traceability because no two parts are alike ? built - in multidrop controller ensures compatibility with other 1 - wire ? net products ? reduce s control, address, data, and power to a single data pin ? directly connects to a single port pin of a microprocessor and communicates at up to 15.3 kbps ? overdrive mode boosts communication speed to 125 kbps ? low - cost 6 - lead tsoc surface - mount package or solder - bumped ucsp? package ? reads and writes over a wide voltage range of 2.8v to 5.25v from - 40c to +85c pin configurations tsoc (150 mils) 6 nc 5 nc 4 nc gnd 1 1 - wire 2 nc 3 ucsp (top view with laser mark, contacts not visible) a2 = 1 - wire a3 = gnd all other bumps: nc yywwrr = date/revision ###xx = lot number refer to the package reliability report for important guidelines on qualified usage conditions. a b c 1 2 3 4 a1 mark ds2432 yyww rr ###xx ordering information part temp range pin - package ds2432p+ - 40c to +8 5c 6 tsoc ds2432p+t&r - 40c to +85c 6 tsoc ds2432x - s+ - 40c to +85c 8 ucsp (2.5k pcs, t&r) + denotes a lead (pb) - free/rohs - compliant package. t&r = tape and reel. request full data sheet at: www.maxim - ic .com/fullds/ds2432 1- wire is a registered trademark of maxim integrated products, inc . top view 219 - 0003; rev 3/12 ds2432 1kb protected 1 - wire eeprom with sha - 1 engine abridged data sheet
abridged data sheet ds2432 2 of 17 description the ds2432 combines 1024 bits of eeprom, a 64 - bit secret, an 8 - byte register/control page with up to five user read/write bytes, a 512 - bit sha - 1 engine, a nd a fully - featured 1 - wire interface in a single chip. each ds2432 has its own 64 - bit rom registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. data is transferred serially via the 1 - wi re protocol, which requires only a single data lead and a ground return. the ds2432 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory, the register page or when installing a new secret. data is first written to the scratchpad from where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to its final memory location, provided that the ds2432 receives a matching 160 - bit mac. the computation of the mac involves the secret and additional data stored in the ds2432 including the devices registration number. only a new secret can be loaded without providing a mac. the sha - 1 engine can also be activated to compute 160- bit message authentication codes (mac) when reading a memory page or to compute a new secret, instead of loading it. applications of the ds2432 include intellectual property security, after - market management of consumables, and tamper - proof data carriers . overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2432. the ds2432 has five main data components: 1) 64 - bit lasered rom, 2) 64 - bit scratchpad, 3) four 32 - byte pages of eeprom, 4) 64 - bit register page, 5) 64 - bit secrets memory , and 6) a 512 - bit sha - 1 engine (sha = secure hash algorithm). the hierarchical structure of the 1 - wire protocol is shown in figure 2. the bus master must first provide one of the seven rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) sk ip rom, 5) resume communication, 6) overdrive - skip rom or 7) overdrive - match rom. upon completion of an overdrive rom command byte executed at regular speed, the device will enter overdrive mode where all subsequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory and sha - 1 functions become accessible and the master may provide any one of the seven memory function commands . the protocol for these memory function commands is described in figure 7 * . all data is read and written least significant bit first. * for figure 7, refer to the full version of the data sheet.
abridged data sheet ds2432 3 of 17 ds2432 block diagram figure 1 parasite power 1 - wire net 64 - bit lasered rom 1 - wire function control secrets memory 64 bits 64 - bit scratchpad data memory 4 pages of 256 bits each crc - 16 generator memory and sha - 1 function control unit 512 - bit secure hash algorithm engine register page 64 bits
abridged data sheet ds2432 4 of 17 64- bit lasered rom each ds2432 contains a unique rom code that is 64 bits long. the first eight bits are a 1 - wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 3.) the 1 - wire crc is generated using a polynomial generator consisting of a s hift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1- wire cyclic redundancy check is available in application note 27. the shift register bits are initialized to zero. then starting with t he least significant bit of the family code, one bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains th e crc value. shifting in the eight bits of crc should return the shift register to all zeros. hierarchcal structure for 1 - wire protocol figure 2 1 - wire net other devices bus master ds2432 available commands: command level: data field affected: 1 - wire rom function commands (see figure 9) ds2432 - specific memory function commands (see f igure 7) read rom match rom search rom skip rom resume overdrive skip overdrive match 64 - bit reg. #, rc - flag 64 - bit reg. #, rc - flag 64 - bit reg. #, rc - flag rc - flag rc - f lag rc - flag, od - flag 64 - bit reg. #, rc - flag, od - flag for details see the full version of the data sheet. 64- bit lasered rom figure 3 msb lsb 8 - bit crc code 48- bit serial number 8 -b it family code * msb lsb msb lsb msb lsb * for the actual family code value, refer to the full version of the data sheet.
abridged data sheet ds2432 5 of 17 1 - wire crc generator figure 4 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data memory map the ds2432 has four memory areas: data memory, secrets memory, register page with special function registers and user - bytes, and a scratchpad. the data memory is organized in pages of 32 bytes. secret, register page and scratchpad are 8 bytes each. the scratchpad acts as a buffer when writing to the data memory, loading the initial secret or when writing to the register page. for further details (including figure 5) refer to the full version of the data sheet. address registers and transfer status the ds2432 employs three address registers: ta1, ta2 and e/s (figure 6). these registers are common to many other 1 - wire devices but operate slightl y differently with the ds2432. registers ta1 and ta2 must be loaded with the target address to which the data will be written or from which data will be read. register e/s is a read - only transfer - status register, used to verify data integrity with write co mmands. since the scratchpad of the ds2432 is designed to accept data in blocks of eight bytes only, the lower three bits of ta1 will be forced to 0 and the lower three bits of the e/s register (ending offset) will always read 1. this indicates that all th e data in the scratchpad will be used for a subsequent copying into main memory or secret. bit 5 of the e/s register, called pf or partial byte flag, is a logic - 1 if the number of data bits sent by the master is not an integer multiple of 8 or if the dat a in the scratchpad is not valid due to a loss of power. a valid write to the scratchpad will clear the pf bit. bits 3, 4 and 6 have no function; they always read 1. the partial flag supports the master checking the data integrity after a write command. th e highest valued bit of the e/s register, called aa or authorization accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag. addres s registers figure 6 bit # 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 (0) t1 (0) t0 (0) target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 1 pf 1 1 e2 (1) e1 (1) e0 (1)
abridged data sheet ds2432 6 of 17 writing with verification to write data to the ds2432, the scratchpad has to be used as intermediate storage. first the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpa d. note that writes to data memory must be performed on 8 - byte boundaries with the 3 lsbs of the target address (t2..t0) equal to 000b. if t2..t0 are sent with non - zero values, the device will set these bits to zero and will write to the modified address u pon completion of the command sequence. in addition, the entire 8 - byte scratchpad will be copied to memory when commanded, therefore eight bytes of data should be written into the scratchpad to ensure that the data to be copied is known. under certain cond itions (see the write scratchpad command) the master will receive an inverted crc - 16 of the command, address (actual address sent) and data at the end of the write scratchpad command sequence. note that the crc is calculated based on the actual target addr ess sent and not the modified address in the case of a non - zero t2..t0. knowing this crc value, the master can compare it to the value it has calculated itself to decide if the communication was successful and proceed to the copy scratchpad command. if the master could not receive the crc - 16, it should send the read scratchpad command to verify data integrity. as preamble to the scratchpad data, the ds2432 repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is s et, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag together with a cleared pf flag indicates that the device did not recognize the write command. if everything went correctly, both flags are cleared. now the master can continue reading and verifying every data byte. after the master has verified the data, it can send the copy scratchpad command, for example. this command must be followed exactly by the data of the three address registers ta1, ta2 and e/s. the master should obtain the contents of these registers by reading the scratchpad. memory and sha - 1 function commands this section describes the commands and flow charts to use the memory and sha - 1 engine of the device. it includes tables 1 to 4 and figure 7. please refer to the full version of the data sheet. sha - 1 computation algorithm the sha - 1 c omputation is adapted from the secure hash standard sha - 1 document as it can be downloaded from the nist website ( http://www.itl.nist.gov/fipspubs/fip180 - 1.htm). further details are found in the full version of the data sheet. 1 - wire bus system the 1 - wi re bus is a system, which has a single bus master and one or more slaves. in all instances the ds2432 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configurati on, transaction sequence, and 1 - wire signaling (signal types and timing). a 1 - wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master.
abridged data sheet ds2432 7 of 17 hardware configuration the 1 - wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1 - wire bus must have open drain or 3 - state outputs. the 1 - wire port of the ds2432 is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1 - wire bus with multiple slaves attached. at regular speed the 1 - wire bus has a maximum data rate of 15.3 kbps. the spee d can be boosted to 125 kbps by activating the overdrive mode. the ds2432 requires a 1 - wire pullup resistor of maximum 2.2 k ? for executing any of its memory and sha - 1 function commands at any speed. when communicating with several ds2432 simultaneously, e. g., to install the same secret in several devices, the resistor should be bypassed by a low - impedance pullup to v pup while the device transfers data from the scratchpad to the eeprom. the idle state for the 1 - wire bus is high. if for any reason a transact ion needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 s (overdrive speed) or more than 120 s (regular speed), one or more devices on the bus may be reset. hardware configuration figure 8 open drain port pin rx = receive tx = transmit 100 ? mosfet v pup rx tx tx rx data r pup bus master ds2432 1 - wire port i l transaction sequence the protocol for accessing the ds2432 via the 1 - wire port is as follows: ? initialization ? rom function command ? memory or sha - 1 function command ? transaction/data i nitialization all transactions on the 1 - wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets t he bus master know that the ds2432 is on the bus and is ready to operate. for more details, see the 1- wire signaling section.
abridged data sheet ds2432 8 of 17 rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands that the ds2432 supports. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the ds2432 s 8 - bit family code, unique 48 - bit serial number, and 8 - bit crc. this command should only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired - and result). the r esultant family code and 48 - bit serial number read by the master will be invalid. match rom [55h] the match rom command, followed by a 64 - bit registration number, allows the bus master to address a specific ds2432 on a multidrop bus. only the ds2432 that exactly matches the 64 - bit registration number will respond to the following memory function command. all other slaves will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. search rom [f0h] when a system is in itially brought up, the bus master might not know the number of devices on the 1- wire bus or their 64 - bit registration numbers. the search rom command allows the bus master to use a process of elimination to identify the 64 - bit numbers of all slave device s on the bus. the search rom process is the repetition of a simple 3 - step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this 3 - step routine on each bit of the registration number. aft er one complete pass, the bus master knows the 64 - bit number of one device. additional passes will identify the registration numbers of the remaining devices. refer to application note 187 for a detailed discussion of a search rom, including an actual exam ple. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access the memory and sha - 1 functions without providing the 64 - bit registration number. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open - drain pulldowns will produce a wired - and result). overdrive skip rom [3ch] on a single - drop bus this command ca n save time by allowing the bus master to access the memory and sha - 1 functions without providing the 64 - bit registration number. unlike the normal skip rom command the overdrive skip rom sets the ds2432 in the overdrive mode (od = 1). all communication fo llowing this command code has to occur at overdrive speed until a reset pulse of minimum 480 s duration resets all devices on the bus to regular speed (od = 0). when issued on a multidrop bus this command will set all overdrive - supporting devices into ov erdrive mode. to subsequently address a specific overdrive - supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this will speed up the search process. if more than one overdrive - suppor ting slave is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired - and result).
abridged data sheet ds2432 9 of 17 rom functions flow ch art figure 9 from figure 9 2 nd part to memory and sha - 1 functions flow chart (figure 7) master tx bit 0 master tx bit 63 master tx bit 1 bit 63 match ? rc = 0 ds2432 tx bit 0 ds2432 tx bit 0 master tx bit 0 ds2432 tx bit 1 ds2432 tx bit 1 master tx bit 1 ds2432 tx bit 63 ds2432 tx bit 63 master tx bit 63 rc = 1 bit 1 match ? bit 0 match ? y n y n y n bit 63 match ? rc = 0 rc = 1 bit 1 match ? b it 0 match ? y n y n y n rc = 0 ds2432 tx crc byte ds2432 tx seria l number (6 bytes) ds2432 tx family code (1 byte) rc = 0 to figure 9 2 nd part n f0h search rom command ? n 55h match rom command ? n cch skip rom command ? y y y y n 33h read rom command ? to figure 9 2 nd part bus master tx rom function command ds2432 tx presence pulse od reset pulse ? n y od = 0 bus master tx reset pulse from figure 9, 2 nd part from memory and sha - 1 functions flow chart (figure 7)
abridged data sheet ds2432 10 of 17 rom functions flow chart (continued) figure 9 to figure 9 1 st part from figure 9 1 st part from figure 9 1 st part to figure 9, 1 st part y n a5h resume command ? rc = 1 ? y n 3ch overdrive skip rom ? rc = 0 ; od = 1 master tx reset ? y n n y master tx reset ? n y master tx bit 0 master tx bit 63 master tx bit 1 bit 63 match ? rc = 0 ; od = 1 rc = 1 bit 1 match ? y n y n bit 0 match ? y n y n 69h overdrive match rom ?
abridged data sheet ds2432 11 of 17 overdrive match rom [69h] the overdrive match rom command, followed by a 64 - bit registration number transmitted at over drive speed, allows t he bus master to address a specific ds2432 on a multidrop bus and to simultane ously set it in overdrive mode. only the ds2432 that exactly matches the 64 - bit number will respond to the subsequent memory or sha - 1 function command. slaves already in overdri ve mode from a previous overdrive skip or a successful overdrive match command will remain in overdrive mode. all over - drive - capable slaves will return to regular speed at the next reset pulse of minimum 480 s duration. the overdrive match rom command can be used with a single or multiple devices on the bus. resume command [a5h] in a typical application the ds2432 needs to be accessed several times to write a full 32 - byte page. in a multidrop environment this means that the 64 - bit registration number of a match rom command has to be repeated for every access. to maximize the data throughput in a multidrop environment the resume command function was implemented. this function checks the status of the rc bit and, if it is set, directly transfers control to t he memory and sha - 1 functions, similar to a skip rom command. the only way to set the rc bit is through successfully executing the match rom, search rom or overdrive match rom command. once the rc bit is set, the device can repeatedly be accessed through t he resume command function. accessing another device on the bus will clear the rc bit, preventing two or more devices from simultaneously responding to the resume command function. 1 - wire signaling the ds2432 requires strict protocols to ensure data int egrity. the protocol consists of four types of sig - naling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1 and read data. except for the presence pulse the bus master initiates all these signals. the ds2432 can communicate at two different speeds, regular speed and overdrive speed. if not explicitly set into the overdrive mode, the ds2432 will communicate at regular speed. while in overdrive mode the fast timing applies to all waveforms. the initialization sequence require d to begin any communication with the ds2432 is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds2432 is ready to send or receive data. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s at regular speed, 48 s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1 - wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the ds2432 waits (t pdh , 15 - 60 s at regular spee d, 2 - 6 s at overdrive speed) and then transmits the presence pulse (t pdl , 60- 240 s at regular speed, 8 - 24 s at overdrive speed). a reset pulse of 480 s or longer will exit the overdrive mode returning the device to regular speed. if the ds2432 is in ov erdrive mode and the reset pulse is no longer than 80 s the device will remain in overdrive mode.
abridged data sheet ds2432 12 of 17 initialization procedure ?r eset and prese nce pulses? figure 10 v pullup v pullup min v ih min v il ma x 0 v resistor master ds2432 t r t rstl t pdl t rsth t pdh master tx ?reset pulse? master rx ?presence pulse? read/write time slots the definitions of write and read time slots are illustra ted in figure 11. the master initiates all time slots by driving the data line low. the falling edge of th e data line synchronizes th e ds2432 to the master by triggering an internal dela y circuit. during write time slots, the de lay circuit determines when the ds2432 will sample the data line. for a read data time sl ot, if a ?0? is to be transmitted, the delay circuit determines how long the ds2432 will hold the data line lo w. if the data bit is a ?1?, the ds2432 will not hold the data line low at all. read/write timing diagram figure 11 write-one time slot v pullup v pullup min v ih min v il ma x 0 v t low1 15 s (od: 2 s) 60 s (od: 6 s) ds2432 sampling window t rec t slot resistor master write-zero time slot v pullup v pullup min v ih min v il ma x 0 v resistor master t low0 15 s (od: 2 s) 60 s (od: 6 s) ds2432 sampling window t rec t slot
abridged data sheet ds2432 13 of 17 read/write timing diagram figure 11 (continued) read-data time slot v pullup v ih min v pullup min v il max 0v t lowr t rec t slot master * sampling window t su t rdv t release resistor master ds2432 *the optimal sampling point for the master is as close as possible to the end time of the t rdv period without exceeding t rdv . for the case of a read-one time slot, th is maximizes the amount of time for the pullup resistor to recover the line to a high level. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire device releases the line (t release = 0). crc generation with the ds2432 there are two different types of crcs (cyclic redundancy checks). one crc is an 8-bit type. it is computed at the factory and lasere d into the most significant byte of the 64-bit rom. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. to determine whether the rom data has been read without error the bus master can compute the crc value from the first 56 bits of the 64-bit rom and compare it to the value read from the ds 2432. this 8-bit crc is received in the true form (non-inverted) when reading the rom. the other crc is a 16-bit type, wh ich is used for erro r detection with memory and sha-1 function commands. for details (including fi gure 12), refer to the full ve rsion of the data sheet.
abridged data sheet ds2432 14 of 17 absolute maximum ratings voltage range on any pin relative to ground - 0.5v to +5.5v operating temperature range - 40 c to +85 c storage temperature range - 55 c to +125 c lead temperature (tsoc only; soldering, 10s) +300 c soldering temperature (reflow) +260 c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time ma y affect reliability . dc electrical characteristics (t a = - 40c to +85c.) parameter symbol min typ max units notes 1 - wire pullup voltage v pup 2.8 5.25 v 1, 2 1 - wire input high v ih 2.2 v 1, 3 1 - wire input low v il - 0.3 0.3 v 1 1 - wire output low at 4ma v ol 0.4 v 1 input load current i l 5 a 4 programming current i lprog 500 a 5 , 6 sha - 1 computation current i csha refer to the full version of data sheet. capacitance (t a = +25c.) parameter symbol min typ max units notes 1 - wire i/o c in/out 100 800 pf 7 e eprom (v pup = 5.0v, t a = +25c.) parameter symbol min typ max units notes write/erase cycles n cycle 50k data retention (at 85c) t dret 10 years ac electrical characteristics : regular speed (v pup = 2.8v to 5.25v, t a = - 40c to +85 c.) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 1 15 s write 0 low time t low0 60 120 s read low time t lowr 1 15 s read data valid t rdv 15 s 8 release time t release 0 15 45 s read data se tup t su 1 s 9 recovery time t rec 5 s 1 0 reset high time t rsth 480 s reset low time t rstl 480 s 11 presence detect high t pdhigh 15 60 s 12 presence detect low t pdlow 60 240 s 12 programming time t prog 10 ms sha - 1 computation time t csha refer to the full version of data sheet.
abridged data sheet ds2432 15 of 17 ac electrical characteristics : overdrive speed (v pup = 2.8v to 5.25v, t a = - 40c to +85c.) parameter symbol min typ max units notes time slot t slot 6 16 s write 1 low time t low1 1 2 s write 0 low time t low0 6 16 s read low time t lowr 1 2 s read data valid t rdv 2 s 8 release time t release 0 1.5 4 s read data setup t su 1 s 9 recovery time t rec 2 s 1 0 reset high time t rsth 48 s reset low time t rstl 48 80 s presence detect high t pdhigh 2 6 s presence detect low t pdlow 8 24 s programming time t prog 10 ms sha - 1 computation time t csha refer to the full version of data sheet. notes: 1. all voltages are referenced to ground. 2. v pup = external pullup v oltage, see figure 8. 3. v ih is a function of the external pullup resistor and v pup . 4. input load is to ground. 5. during write operations to the eeprom the voltage on the 1 - wire bus must not fall below 2.8v. 6. guaranteed by design, not production tested. 7. capacitanc e on the data pin could be 800 pf when power is first applied. once the parasite capacitance is charged, it does not affect normal communication. 8. the optimal sampling point for the master is as close as possible to the end time of the t rdv period without exceeding t rdv . for the case of a read - one time slot, this maximizes the amount of time for the pu llup resistor to recover the line to a high level. for a read - zero time slot it ensures that a read will occur before the fastest 1 - wire device releases the line (t release = 0). 9. read data setup time refers to the time the host must pull the 1 - wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge. 10. the minimum recovery times of 5s (regular speed) and 2s (overdrive speed) apply over the full voltage and temperature range. recovery times as short as 1s (regular and over drive speed) should be acceptable in existing or legacy designs with v pup = 5v 5%. recovery times shorter than those in the electrical characteristics table are not recommended for new designs. 11. the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 12. the first presence pulse after power - up could be outside the t pdhighmax to (t pdhighmin + t pdlowmin ) interval, but will be complete within 2ms after power - up.
abridged data sheet ds2432 16 of 17 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertai ns to the package regardless of rohs status. package type package code ou tline no. land pattern no. 6 tsoc d6+1 21-0382 90-0321 8 ucsp br823+1 21-0373 refer to application note 1891
abridged data sheet ds2432 17 of 17 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir c uit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 201 2 maxim integrated pr oducts maxim is a registered trademark of maxim integrated products. revision history revision date descr iption pages changed 040907 initial release. 060608 removed the leaded parts from the ordering information table and corrected package name from csp to ucspr. 1 removed 64 - bit registration number from overdrive skip rom in figure 2. 4 removed refe rence to tamper detect register (does not exist). 7 in figure 8, changed 5 a typ to i l . 7 in the dc electrical characteristics table, added the 1 - wire pullup voltage parameter (v pup ) (moved from the headline into the table) and removed the 1 - wire o utput high parameter (v oh ). in the eeprom table, added (at +85 c) to the data retention parameter. 14 added package information section. 16 minor nontechnical corrections to the text (various pages). 1, 2, 4, 8, 15 2/10 electrical characteristics tabl e: t recmin changed from 1s to 5s (regular speed) and 2s (overdrive speed); v ilmax changed from tbd to 0.3v; sha - 1 computation current added. 14, 15 ucsp package outline deleted; see section package information to access the latest drawing. 16 typ o - and style corrections various pages original note 8 deleted from ec table notes and remaining notes renumbered to conform to style guide. 14, 15 3/12 deleted ds2432x+ from the ordering information table . 1 updated the soldering information and adde d the lead temperature to the absolute maximum ratings . 14 added note 12 to ac electrical characteristics: regular speed table parameters t pdhigh and t pdlow . 14 revised the electrical characteristics tables note 7 . 15 added the land pattern column to the package information table . 16

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